Modern electronic systems often operate using digital logic. Digital logic is usually characterized by two distinct states which represent a Boolean one and a Boolean zero. However, since there are many different families of electronic devices, each family, or group of families, may define the two logic states at different voltage levels.
For example, a device from a first family may operate with a logic "1" value represented by a 3.2 volt level and a logic "0" value represented by a 0 volt level. The voltage difference between the two signals is the voltage swing, which in this case is 3.2 volts. A device from a second family, on the other hand, may operate with a logic "1" value represented by a 2.4 volt level and a logic "0" value represented by a 1.6 volt level. The voltage swing in this case is 0.8 volts.
There are many situations in which the first device with logic levels of 3.2 volts and 0 volts must communicate with the second device with logic levels of 2.4 volts and 1.6 volts. To do this, the logic levels for one device must be converted to the logic levels of the other device.
If a first device of a first family is considered device A and a second device of a second family is device B, and device A is to communicate with device B, it is necessary to convert the logic levels for device A to those for device B. Therefore, for device A to have its logic signals accepted by device B, its logic "1" value with a 3.2 volt level must be converted down to a 2.4 volt level, and the logic "0" value with a 0 volt level must be converted up to a 1.6 volt level. These conversions will provide the proper logic levels and voltage swing. As such, the voltage swing must be attenuated by 4 from 3.2 volts to 0.8 volts, and the level shifted up by 1.6 v.
Device A's logic "1" value and logic "0" value voltage levels are converted according to the expression: ##EQU1## where,
a=Device A's logic "1" value level of 3.2 volts or logic "0" level of 0 volts.
According to expression (1), the 3.2 volts will convert to 2.4 volts, and the 0 volts will convert to 1.6 volts. A circuit with a network of resistors is used to do this. Such a circuit attenuates the voltage swing, and performs level shifting through the use of a power supply. Accordingly, the converted logic levels are a function of the power supplies driving devices A and B, as well as the signal level generated by device B.
Referring to FIG. 1, a prior art voltage level shifting circuit is shown generally at 1. Device A 2 has a logic "1" value with a 3.2 volt level and a logic "0" value with a 0 volt level. Device B 30 has a logic "1" value with a 2.4 volt level and a logic "0" value with a 1.6 volt level. The portion of the circuit of the present invention in device A 2 has an open source output stage 3. Open source output stage 3 may be a P-channel field effect transistor ("FET"), such as FET 16. Assuming that it is desirable for device A to communicate with device B, the circuit of FIG. 1 will convert the logic levels and permit this communication. To perform the conversion, the voltage level to be converted is input at input 4. Assuming that the first input at input 4 is logic high, 3.2 volts, FET 6, which has a negative/true gate input, will not conduct. However, when the 3.2 volts is applied to the gate input of FET 8, it will conduct.
When FET 8 conducts, line 14 which connects to the gate input of FET 16 (at open source output stage 3) connects to ground 12. Since line 14 now connects to ground 12, the gate input of FET 16 is pulled to 0 volts. The gate input of FET 16 is negative/true, so FET 16 will conduct. When FET 16 conducts, the supply voltage at 10, 3.2 volts, is supplied to R1 resistor 20 which is disposed between the device A 2 and device B 30.
At device B 30, the supply voltage at 32, 1.6 volts, is input to R2 resistor 44. As stated, FET 16 is conducting, so the supply voltage at 10, 3.2 volts, is applied to R1 resistor 20. Now, the voltage contribution from device A must be determined to see if the proper conversion is taking place when FET 16 is conducting.
When FET 16 is conducting, current I.sub.a flows through R1 resistor 20 and R2 resistor 44. Therefore, current I.sub.a is determined by the expression: ##EQU2## The 16 ma of current flowing through R2 resistor 44 will produce a voltage drop according to the expression: EQU V=IR=(16 ma) (50 .OMEGA.)=0.8 volts (3)
Therefore, at V.sub.b 46, the voltage is 1.6 volts+0.8 volts =2.4 volts. Accordingly, the conversion from the 3.2 volt logic high of device A to 2.4 volts logic high of device B is confirmed.
In the situation when a logic low of 0 volts is applied at input 4 at device A 2, FET 6 will conduct and FET 8 will not conduct. When FET 6 conducts, the supply voltage at 10, 3.2 volts, is supplied to line 14. This applies a logic high to the negative/true gate input to FET 16. Since the gate input is a negative/true, a logic low will be applied to FET 16 and FET 16 will not conduct. If FET 16 does not conduct, device A 2 will not make any voltage contribution at V.sub.b 46 and the voltage at this point is only the 1.6 volts provided by supply 32. Hence, when input at input 4 of device A 2 is a logic low of 0 volts, the valid output at 50 is 1.6 volts which is the logic low for device B 30.
The disadvantages of using the prior art circuit shown in FIG. 1 for carrying out the conversion function is its dependence of the output voltage levels of both power supplies 10 and 32, and the fact that as the ambient temperature and power supply of device B change, the signal levels and voltage thresholds of device B do not generally track these changes in the power supply voltages.
The present invention provides a circuit that overcomes these and other problems as will be set forth in the remainder of the specification referring to the drawings.